The present invention relates to semiconductor processing, and more particularly to a process for forming a blanket dielectric layer to fill gaps between device elements.
In the manufacturing of semiconductor devices, as the dimensions have shrunk, it has become more challenging to provide dielectric film layers that provide adequate electrical isolation between interconnect features and device components in order to minimize RC delay and crosstalk. One method of doing this is to provide dielectric layers using materials having lower dielectric constants (low-k dielectrics) than conventional dielectric materials such as silicon dioxide (SiO2) or silicon nitride. Low-k dielectrics typically have dielectric constants below about 4, where air has a dielectric constant of 1.
In particular, at the start of the fabrication of a back end of line (BEOL) module which contains the interconnect metal levels, a dielectric layer is typically provided between the devices or features, such as gate conductor stacks, on the substrate, or front end of line (FEOL), and the first layer of metal in the interconnect level or BEOL. This dielectric layer between the device level and the interconnect level is known as the pre-metal dielectric (PMD). The process of forming this PMD is referred to hereinafter as a middle of line process, or MOL process, as opposed to the BEOL processes used to form the intermetal dielectrics (IMD) that separate the metal layers.
Methods of depositing low-k dielectric blanket layers have included spin-on, chemical vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PECVD), with PECVD more recently preferred. PECVD processes include the use of organosilicon precursors, such as methylsilane (1MS), trimethyl silane (3MS) and tetramethylsilane (4MS), with various oxidizers. However, the CVD processes, in particular PECVD, may not adequately fill the spaces or gaps between existing metal features, and may leave voids in the dielectric blanket layer which can cause problems such as micro-cracking, lack of structural support, trapping of gases or moisture or allow subsequent metal fill processes to connect nearby voids which can result in shorted device elements. Although films provided by spin-on deposition may adequately fill spaces or gaps, these films are usually porous and would be incompatible with other MOL processing steps by being susceptible to problems such as those mentioned above. The problem of adequate gap fill can be particularly difficult if the aspect ratio (AR), which is the ratio of height to width of the gaps, is above about 1.0. For example, referring to FIG. 1, device structures 130 are formed over a doped region 120 on a substrate 110. The device structures 130, such as gate conductor stacks, are separated by width W and each have height H. Therefore the gap 160 separating the device structures 130 has an aspect ratio (AR) of H/W. If H is greater than W, then the AR is greater than 1 and a blanket dielectric layer 140 formed by a conventional PECVD process will not completely fill the gap 160, leaving a void 150, which can cause problems such as structural and electrical defects as mentioned above.
PECVD methods for depositing low-k dielectric layers for BEOL levels have been suggested which use a carbon-containing precursor, for example, a cyclosiloxane such as tetramethylcyclo-tetrasiloxane (TMCTS) or methylsilanes, with oxygen. Low-k dielectrics will also be required at the MOL level. PECVD can provide deposition rates which are fast enough (in the range of 100""s to 1000""s xc3x85/min) for BEOL applications which must operate at temperatures below about 400xc2x0 C., and as low as 300xc2x0 C., because of the presence of metal features. However, PECVD solutions at the MOL level are not easily utilized, because PECVD processes may leave voids in high aspect ratio gaps, where the gap AR exceeds about 1.0. In addition, plasma processing is not a preferred fill method for MOL as it may cause charge damage to gate oxides.
Thermal CVD processes do not require the use of plasmas to deposit dielectric layers. Sub-atmospheric thermal CVD (SACVD) and low pressure thermal CVD have been used for providing conformal deposition of dielectrics, in which O3 and O2 are respectively used as oxidizing agents. The pressure in SACVD is in the range from about 50 to 800 Torr, and usually between about 200 to 760 Torr. Low pressure CVD typically involves pressures below about 10 Torr. Low pressure CVD will not provide good gap filling results for chemistry such as oxygen plus an organometallic or organosilicon precursor such as TMCTS. Good gap filling typically results through the use of SACVD at pressures above about 200 Torr, and more likely above about 600 Torr. However, using low-k materials for AR greater than 1, SACVD may also leave voids depending on the shape of the gap to be filled.
It would be desirable to use a post-deposition glass reflow step at a low reflow temperature to fill voids left after deposition of a low-k film with minimal heat treatment to avoid thermal damage. For example, in the case of conventional (high-k) dielectric films where controlling the dielectric constant has not been a design requirement, it is known that the addition of dopants may lower the temperature required to reflow the film. However, because the process conditions for depositing low-k films that would also provide good gap-filling results are quite sensitive to the composition of reactant gases and the structure of the gaps to be filled, the addition of dopants which reduce the reflow temperature would not necessarily preserve the desired low-k and gap-filling properties of the film, and may require significant experimentation to achieve the desired results.
Thus, there is a need for a non-plasma low-k oxide CVD process that can provide good gap-filling results for AR greater than 1, that avoids charge damage, that can getter alkali elements, that can be reflowed with minimal heat treatment to avoid thermal damage to the underlying device elements, and that provides a film having the desired low-k property.
Sukharev (U.S. Pat. No. 5,710,079, hereinafter, the Sukharev patent) discloses a method for depositing silicon dioxide films to prevent the formation of voids in gaps by CVD with an organometallic compound, such as tetraethylorthosilicate (TEOS), BPTEOS, TEB, TMOP, OMCTS, HMDS, TMCTS, or TRIES, and which includes ozone and the use of ultraviolet radiation (UV) to increase the deposition rate by increasing the concentration of hydroxyl radicals in order to avoid the formation of voids and improve gap-fill. However, the increased concentration of hydroxyl radicals may lead to a porous film that is incompatible with MOL processing and increased concentration of hydroxyl radicals will result in reduced carbon incorporation in the film. Since carbon incorporation is required to achieve a low-k oxide, the Sukarev patent does not provide a solution for depositing low-k dielectric films that provide good gap filling results. Moreover, the use of UV radiation to increase deposition rates may require modification of standard reaction chambers and may increase the cost of processing.
Yuan (U.S. Pat. No. 5,855,957, hereinafter, the Yuan patent) discloses a method for depositing an oxide thin film using an atomospheric pressure thermal CVD (APCVD) process including ozone (O3) which can provide uniform step coverage. The Yuan patent discloses the use of precursors such as tetraethoxysilane (TEOS), hexamethyldisilazane (HMDSO), octamethylcyclotetrasiloxane (OMCTS), 2,4,6,8-tetramethylcyclotetrasiloxane (TMCTS), substances of the general formula SiHx(OR)4-x where xe2x80x9cRxe2x80x9d is an alkyl group or its oligomers and x=0, 1, 2, or 3, and other chemicals such as boron, phosphorous, fluorine containing sources and combinations thereof. The method of the Yuan patent discloses that uniform step coverage or gap fill can be provided for AR up to about 3. In addition, the preferred embodiment of the Yuan patent requires movement of the wafer through the reactor, which adds to the complexity of the reactor design. Movement of the wafer also results in variation in elemental composition with depth across the substrate and therefore the etch rate will vary with depth, which is incompatible with MOL processing steps such as wet HF etch. In addition, the Yuan patent is not directed to the deposition of low-k dielectric films, which would require strict compositional and density control that is beyond the capability of the Yuan patent.
Saito (U.S. Pat. No. 5,545,436, hereinafter, the Saito patent) discloses an atmospheric CVD method including O3 for depositing an undoped silicon oxide film using a precursor such as TEOS, OMCTS, tetra propoxy silane (TPOS), or TMCTS. The Saito patent also requires the movement of the wafer relative to the gas injector, adding complexity to the reactor design and suffers from similar compositional deficiencies as in the Yuan patent. Therefore, the Saito patent is not suitable for the deposition of low-k dielectrics that provide good gap-filling for AR greater than about 3.
Rose et al. (U.S. Pat. No. 6,068,884, hereinafter, the Rose patent) discloses a method for depositing a low-k dielectric film using a PECVD process. The Rose patent discloses the use of precursors of organosilicon, such as siloxanes, to form an inorganic/organic hybrid dielectric material having a low-k (less than 4.0, and preferably in the range 3.0 to 1.5) and good thermal stability at temperatures in the range of 425-450xc2x0 C. The precursors disclosed in the Rose patent include organic siloxanes, fluorosiloxanes, cyclosiloxanes, fluorine containing cyclosiloxanes, organosilazanes, fluorosilazanes, cyclosilazane, silicates, TEOS, and TMS and mixtures thereof. Although the Rose patent suggests that either atmospheric, subatmospheric, or low pressure thermal CVD processes may be used, the preferred embodiments of the Rose patent require the use of a plasma CVD process with organosilicon precursors such as hexamethyl disiloxane (HMDSO), 1,1,3,3-tetramethyldisiloxane (TMDSO), TEOS, and OMCTS. Thus, the method of the Rose patent does not recognize the disadvantage of potential charge damage due to the use of plasma CVD processes. The Rose patent also does not solve the problem of gap-fill for AR greater than 1.
Ravi et al. (U.S. Pat. No. 5,976,993, hereinafter, the Ravi patent) discloses a method for depositing silicon oxide films with reduced instrinsic stress which can also provide good gap-fill results using a high density plasma chemical vapor deposition (HDP-CVD) process. Since the Ravi patent teaches the use of a PECVD process and does not suggest the use of a carbon-containing cyclosiloxane precursor such as TMCTS or OMCTS, the Ravi patent is not suitable for depositing low-k dielectric films which have good gap fill characteristics for AR greater than about 1. Also, the method of the Ravi patent suffers from potential charge damage due to plasma processing.
Laboda et al. (EP 0 960 958 A2, hereinafter, the Laboda reference) discloses a method for depositing low-k dielectric films using a plasma enhanced CVD (PECVD) or ozone enhanced CVD process using a methyl-containing silane, such as methylsilane, dimethylsilane, trimethylsilane and tetramethylsilane, and an oxygen providing gas. The Laboda reference also suggests that dopants such as phosphine or diborane, halogens such as fluorine may be used, but does not suggest what advantages such dopants might provide. The Laboda reference also does not recognize the problem of potential charge damage due to plasma processes. In addition, the method of the Laboda reference does not provide good gap-filling characteristics for AR greater than about 1.
In view of the foregoing discussion, there is a need to provide for a method to deposit a low-k dielectric PMD layer that can fill high aspect ratio (AR greater than about 3) gaps without voids, without charge or thermal damage to the semiconductor devices and provides gettering of alkali elements.
The present invention addresses the above-described need by providing a method for depositing a pre-metal low-k dielectric that provides good gap fill, minimizes the formation of voids, and getters alkali elements such as sodium and potassium.
It is the further object of the present invention to provide a method for forming a pre-metal low-k dielectric by a process which will not cause thermal damage to the semiconductor devices by keeping the process temperature within the thermal budget of the devices.
This invention has the further objective of forming a pre-metal low-k dielectric by a process which will not cause charge damage to the semiconductor devices.
According to one aspect of the present invention, a method is provided for forming a pre-metal (PMD) low-k dielectric layer by a thermal sub-atmospheric chemical vapor deposition process including a carbon-containing precursor, ozone, and a source of dopants.
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.